Complex digital integrated circuits (“ICs”) are initially designed using high-level logic elements such as adders, arithmetic/logic units (ALUs), memory units, buses, etc. These high level elements are in turn constructed from lower level components such as AND gates, OR gates, inverters, etc. These lower level components are constructed from basic electronic components such as transistors, diodes, and electrical conductive traces. All of these electronic and circuit components of ICs are jointly referred to as “components.”
Design engineers design an integrated circuit by transforming a circuit description of the integrated circuit into geometric descriptions of physical components that create the basic electronic components. The detailed geometric descriptions of physical components are referred to as integrated circuit layouts.
To create the integrated circuit layout for a complex integrated circuit, circuit design engineers use Electronic Design Automation (“EDA”) application programs. These EDA application programs are computer-based tools for creating, editing, and analyzing integrated circuit design layouts.
It is a layout EDA application program that creates a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit. For instance, EDA tools commonly use rectangular lines to represent the passive wire segments (conductors) that interconnect the active integrated circuit components such as transistors. These EDA tools also represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an initial integrated circuit layout has been created, the integrated circuit layout is tested and optimized using a set of EDA testing tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification are performed to ensure that the integrated circuit layout will perform as desired. The test of extraction is the process of analyzing the geometric layout and material composition of an integrated circuit layout in order to “extract” electrical characteristics of the integrated circuit layout. The step of verification uses the extracted electrical characteristics to analyze the circuit design using circuit analysis tools.
Common electrical characteristics that are extracted from an integrated circuit layout include capacitance and resistance of the various “nets” (electrical interconnects) in the integrated circuit. These electrical characteristics are sometimes referred to as “parasitic” since these electrical characteristics are not intended by the designer but result from the underlying physics of the integrated circuit design.
For example, when an electrical circuit designer wishes to connect two different locations of an integrated circuit with an electrical conductor, the electrical circuit designer would ideally like perfect conductor with zero resistance and zero capacitance. However, the geometry of a real conductor, its material composition, and its interaction with other nearby circuit elements will create some parasitic resistance and parasitic capacitance. The parasitic resistance and parasitic capacitance affect the operation of the designed integrated circuit. Thus, the effect of the parasitic resistance and parasitic capacitance affect must be considered.
To test an integrated circuit layout, the parasitic resistance and parasitic capacitance are “extracted” from the integrated circuit layout and then the integrated circuit is analyzed and possibly simulated using the extracted parasitic resistance and parasitic capacitance. If the parasitic resistance or parasitic capacitance cause undesired operation, then the integrated circuit layout must be changed. Furthermore, minimizing the amount of parasitic resistance and parasitic capacitance can optimize the performance of the integrated circuit.
Extracting the electrical characteristics of the integrated circuit layout (such as capacitance, resistance, and inductance) is an extremely difficult task. Most existing extraction systems approximate sections of an integrated circuit with similar geometric configurations having known electrical characteristics. Interpolation between various different similar geometric configurations is used to further refine extracted electrical characteristics.
The existing extraction techniques have been adequate but are increasingly becoming problematic as the feature size of the electrical components on integrated circuits grow ever smaller. With the very small feature size of current and upcoming semiconductor processes, the accurate extraction of electrical characteristics from integrated circuit layouts becomes critical. Thus, it would be desirable to implement new integrated circuit extraction methods that are both accurate and fast.